I wrote a KiCad plugin to generate Verilog code from a schematic.
Why would anyone want such a thing? In my case, I’m designing a homebrew CPU. I wanted to simulate it before fabricating the PCB. Generating Verilog, and using one of the many Verilog simulators that are available, seemed like the best approach.
There are some Verilog design packages, like Quartus II and Icestudio, that allow you to draw a schematic. But their schematic tools are not as powerful as KiCad’s. And once you’re done drawing and testing in those packages, you need to go through the tedious and error-prone process of re-drawing the schematic in a PCB CAD program anyway.
Unfortunately, my KiCadVerilog plugin is not a one-step solution. It generates a framework for a working Verilog program, with Verilog modules for all the components, and Verilog wires for all the connections. But it doesn’t know the behavior of the components in the schematic. So the user is still responsible for writing Verilog for each component. For example, if there’s a 7402 quad NAND gate in the design, or a 74181 Arithmetic Logic Unit, the user has to write (or find on the web) Verilog code to implement it.
It does some other cool things though: it recognizes pull-up and pull-down resistors, and generates Verilog appropriately; it recognizes bypass capacitors and knows not to generate Verilog code for them; and it provides a mechanism to integrate your Verilog module implementations into the generated code safely, so that you can modify your schematic, re-generate the Verilog, and your implementations will be preserved.
You can find the plugin, along with extensive documentation, on GitHub.
